The operation of a computing device, such as a web server or a smart phone, frequently depends on the timing of a duration of some occurrence. Occurrences can include a communication involving a transmission and a reception, a performance of a procedure, a user input/output (I/O) exchange to provide user output and accept user input, and the like. The duration of an occurrence is defined by an initiating event and a terminating event. Thus, respective examples of corresponding terminating events include a signal arrival, a completion of a procedure, and a detection of user input. Computing devices can convert an occurrence having some duration to a digital representation of the corresponding elapsed time using a time-to-digital converter (TDC).
Conventional TDCs provide a TDC output value from an encoder using a ring oscillator that is coupled to at least two different counters. The ring oscillator includes a series of inverters. The series of inverters changes a ring oscillator output value as a ring oscillator signal propagates along the series of inverters. At the last inverter of the series, the ring oscillator signal is looped back to the first inverter to form the ring oscillator. After the last inverter of the series, the ring oscillator signal is further coupled to an end counter having an end counter value that keeps track of how many times the ring oscillator signal has looped through the ring oscillator.
Conventional TDCs also include multiple flip-flops. Each respective flip-flop of a first set of flip-flops corresponds to a respective inverter of the series of inverters of the ring oscillator. At the termination of an occurrence being timed, a respective flip-flop samples an output of each respective inverter along the series of inverters to obtain the ring oscillator output value. A second set of flip-flops is employed to sample the end counter value from the end counter. The encoder receives the ring oscillator output value via the first set of flip-flops corresponding to the series of inverters and the end counter value via the second set of flip-flops corresponding to the end counter. From the ring oscillator output value and the end counter value, the encoder produces the TDC output value.
However, there is signaling ambiguity between the ring oscillator and the end counter. There is a timing problem for the ring oscillator signal after the last inverter of the ring oscillator and just before the end counter. The arrival of the signal to trigger the end counter is subject to some degree of uncertainty, such as when the time of the terminating event is near the time of triggering the end counter. Consequently, at least one additional, interior counter is included as part of the conventional TDC near the middle of the ring oscillator. This interior counter receives a signal from an interior inverter of the series of inverters to track an interior counter value as a check against the end counter value of the end counter. To decipher which counter currently has a correct counter value, the encoder also includes error correction logic.
Unfortunately, implementing both the interior counter and the error correction logic involves deploying numerous additional circuit devices on a TDC portion of an integrated circuit (IC) chip. These additional circuit devices increase both the cost and the complexity of designing and producing the integrated circuit chip. Further, operating these additional circuit devices generates more heat and increases the power demands of the integrated circuit chip, which together reduce the battery life of the computing device in which the integrated circuit chip is functioning.